• <li id="ccaac"></li>
  • <table id="ccaac"><rt id="ccaac"></rt></table>
  • <td id="ccaac"></td>
  • <td id="ccaac"></td>
  • JEDEC JESD51-8-1999
    集成電路熱測試方法環境條件-Junction-to-Board

    Integrated Circuit Thermal Test Method Environmental Conditions - Junction-to-Board


    JEDEC JESD51-8-1999 發布歷史

    This standard specifies the environmental conditions necessary for determining the junction-to-board thermal resistance, Rejo, and defines this term. The bJBthen nal resistance is a figure of merit for comparing the thermal performance of surface mount packages mounted on a standard board. This specification should be used in conjunction with the overview document JESD5 1, “Methodology for the Thermal Measurement of Component Packages (Single Semiconductor Device)” [i] and the electrical test procedures described in EINJESDS 1- 1, “Integrated Circuit Thermal Measurement Method (Single Semiconductor Device)“ [2]. The environmental conditions described in this document are specifically designed for testing of integrated circuit devices that are mounted on standard test boards with two internal copper planes [3]. This standard is not applicable to packages that have asymmetric heat flow paíhs io the printed circuit board causeá by such thermai enhancements as fused ieacis (ieads connecteci to the die pad) or power style packages with the exposed heat slug on one side of the package.

    JEDEC JESD51-8-1999由(美國)固態技術協會,隸屬EIA US-JEDEC 發布于 1999。

    JEDEC JESD51-8-1999 在中國標準分類中歸屬于: L56 半導體集成電路,在國際標準分類中歸屬于: 31.200 集成電路、微電子學。

    JEDEC JESD51-8-1999的歷代版本如下:

    JEDEC JESD51-8-1999



    標準號
    JEDEC JESD51-8-1999
    發布日期
    1999年
    實施日期
    廢止日期
    中國標準分類號
    L56
    國際標準分類號
    31.200
    發布單位
    US-JEDEC
    適用范圍
    This standard specifies the environmental conditions necessary for determining the junction-to-board thermal resistance, Rejo, and defines this term. The bJBthen nal resistance is a figure of merit for comparing the thermal performance of surface mount packages mounted on a standard board. This specification should be used in conjunction with the overview document JESD5 1, “Methodology for the Thermal Measurement of Component Packages (Single Semiconductor Device)” [i] and the electrical test procedures described in EINJESDS 1- 1, “Integrated Circuit Thermal Measurement Method (Single Semiconductor Device)“ [2]. The environmental conditions described in this document are specifically designed for testing of integrated circuit devices that are mounted on standard test boards with two internal copper planes [3]. This standard is not applicable to packages that have asymmetric heat flow paíhs io the printed circuit board causeá by such thermai enhancements as fused ieacis (ieads connecteci to the die pad) or power style packages with the exposed heat slug on one side of the package.

    JEDEC JESD51-8-1999 中可能用到的儀器設備


    誰引用了JEDEC JESD51-8-1999 更多引用





    Copyright ?2007-2022 ANTPEDIA, All Rights Reserved
    京ICP備07018254號 京公網安備1101085018 電信與信息服務業務經營許可證:京ICP證110310號



  • <li id="ccaac"></li>
  • <table id="ccaac"><rt id="ccaac"></rt></table>
  • <td id="ccaac"></td>
  • <td id="ccaac"></td>
  • 床戏视频